library IEEE;
use IEEE.std_logic_1164.all;
use work.mips_package.all;
use work.mips_package1.all;
use work.mips_package2.all;
use work.mips_package3.all;

entity mips_datapath is
	port(RegWrite, MemToReg : in std_logic;
		IR_in : in std_logic_vector(31 downto 0);
		MDR_in : in std_logic_vector(15 downto 0);
		OP : out std_logic_vector(5 downto 0);
		clk : in std_logic);
end mips_datapath;

architecture structure of mips_datapath is
	signal zero, cout, alwayson : std_logic;
	signal rs,rt,rd : std_logic_vector(4 downto 0);
	signal funct : std_logic_vector(5 downto 0);
	signal wr_data, Reg1, Reg2, aluA, aluB, aluResult, alu_Out : std_logic_vector(15 downto 0);
	signal rsi,rti,rdi : std_logic_vector(1 downto 0);
begin
	rsi <= rs(1 downto 0);
	rti <= rt(1 downto 0);
	rdi <= rd(1 downto 0);
	alwayson <= '1';

	IReg : IR
		port map(IR_in, OP, rs, rt, rd, funct, clk);

	regfile : registerfile
		port map(rsi, rti, rdi, wr_data, Reg1, Reg2, RegWrite);

	ALU : nBitAlu
		port map(aluA,aluB,aluResult,funct(1 downto 0),cout,zero);


	Areg : sixteenbitreg
		port map(Reg1, aluA, alwayson, clk);
	Breg : sixteenbitreg
		port map(Reg2, aluB, alwayson, clk);
	AluOutbus : sixteenbitreg
		port map(aluResult, alu_Out, alwayson, clk);
	dataMux : twoX16mux
		port map(alu_Out, MDR_in, wr_data, memToReg);
	
end structure;



